package rv32isc

import chisel3._
import chisel3.util._

import config.Configs._
import utils._

// Top的模块接口，用于测试
class TopIO extends Bundle {
    val addr = Output(UInt(ADDR_WIDTH.W))
    val inst = Output(UInt(INST_WIDTH.W))
    val bundleCtrl = new BundleControl()
    val resultALU = Output(UInt(DATA_WIDTH.W))
    val rs1 = Output(UInt(DATA_WIDTH.W))
    val rs2 = Output(UInt(DATA_WIDTH.W))
    val imm = Output(UInt(DATA_WIDTH.W))
    val resultBranch = Output(Bool())
    val result = Output(UInt(DATA_WIDTH.W))


    // //这里是顶层接口，需要通过c++去使用
    // val instAddr_io = Input(UInt(ADDR_WIDTH.W))  // 指令地址
    // val inst_io = Output(UInt(INST_WIDTH.W))     // 指令输出
    // val dataAddr_io = Input(UInt(ADDR_WIDTH.W))  // 数据地址
    // val dataIn_io = Input(UInt(DATA_WIDTH.W))    // 数据写入
    // val dataOut_io = Output(UInt(DATA_WIDTH.W))  // 数据读取
    // val bundleMemDataControl_io = new BundleMemDataControl()  // 数据控制信号
}

class Top extends Module {
    val io = IO(new TopIO())

    val pcReg = Module(new PCReg())
    //val memInst = Module(new MemInst())
    val decoder = Module(new Decoder())
    val registers = Module(new Registers())
    val alu = Module(new Alu())
    // val memData = Module(new MemData())
    val controller = Module(new Controller())

    val mem = Module(new MemUnified()) //这里是我需要拉渠道顶层的模块的接口

    // PCReg in
    pcReg.io.resultBranch <> alu.io.resultBranch
    pcReg.io.addrTarget <> mem.io.dataOut
    pcReg.io.ctrlBranch <> controller.io.bundleControlOut.ctrlBranch
    pcReg.io.ctrlJump <> controller.io.bundleControlOut.ctrlJump
    
    // MemInst in
    mem.io.instAddr <> pcReg.io.addrOut

    // Decoder in
    decoder.io.inst <> mem.io.inst

    // Registers in
    registers.io.bundleReg <> decoder.io.bundleReg
    registers.io.ctrlRegWrite <> controller.io.bundleControlOut.ctrlRegWrite
    registers.io.ctrlJump <> controller.io.bundleControlOut.ctrlJump
    registers.io.dataWrite <> mem.io.dataOut
    registers.io.pc <> pcReg.io.addrOut

    // ALU in
    alu.io.bundleAluControl <> controller.io.bundleAluControl
    alu.io.dataRead1 <> registers.io.dataRead1
    alu.io.dataRead2 <> registers.io.dataRead2
    alu.io.imm <> decoder.io.imm
    alu.io.pc <> pcReg.io.addrOut
    
    // MemData in
    mem.io.bundleMemDataControl <> controller.io.bundleMemDataControl
    mem.io.dataIn <> registers.io.dataRead2
    mem.io.dataAddr <> alu.io.resultAlu

    // Controller in
    controller.io.bundleControlIn <> decoder.io.bundleCtrl
    
    // top -->这里是正常的顶层io
    io.addr <> pcReg.io.addrOut
    io.bundleCtrl <> decoder.io.bundleCtrl
    io.inst <> mem.io.inst
    io.result <> mem.io.dataOut
    io.resultALU <> alu.io.resultAlu
    io.resultBranch <> alu.io.resultBranch
    io.imm <> decoder.io.imm
    io.rs1 <> registers.io.dataRead1
    io.rs2 <> registers.io.dataRead2

    //存储器拉到顶层的io
    // //这里是顶层接口，需要通过c++去使用
    // io.instAddr_io <> mem.io.instAddr
    // io.inst_io <> mem.io.inst
    // io.dataAddr_io <> mem.io.dataAddr
    // io.dataIn_io <> mem.io.dataIn
    // io.dataOut_io <> mem.io.dataOut
    // io.bundleMemDataControl_io <> mem.io.bundleMemDataControl

}

